Character generator for a high resolution dot matrix display

ABSTRACT

A character generator for a dot-matrix type alpha-numeric display device whereby the resolution of the characters to be displayed is greatly increased without a corresponding increase in the size of the Read-Only Memory (ROM) utilized to store the dot patterns defining the characters to be formed. This result is accomplished by providing circuitry external to the ROM which quadruples the number of dots normally comprisiing an alphanumeric character. In addition, a smoothing circuit is provided which causes predetermined dots in the dot-matrix to be illuminated or extinguished so as to improve the overall continuity of the dot patterns defining the characters, yielding a more pleasing representation of those characters.

[ Nov. 18, 1975 CHARACTER GENERATOR FOR A HIGH RESOLUTION DOT MATRIX DISPLAY [75] Inventor: Bruce M. Anderson, New Brighton,

Minn.

[73] Assignee: Sperry Rand Corporation, New

York, NY.

[22] Filed: June 3, 1974 [21] Appl. No.: 475,724

OUTPUT SELECTOR SMOOTHING CIRCUIT (FIG. 8)

DISABLE DETECT CIRCUIT Primary Examiner-David L. Trafton Attorney, Agent, or FirmThomas J. Nikolai; Kenneth T. Grace; Marshall M. Truex [57] ABSTRACT A character generator for a dot-matrix type alpha numeric display device whereby the resolution of the characters to be displayed is greatly increased without a corresponding increase in the size of the Read-Only Memory (ROM) utilized to store the dot patterns defining the characters to be formed. This result is accomplished by providing circuitry external to the ROM which quadruples the number of dots normally comprisiing an alpha-numeric character. In addition, a smoothing circuit is provided which causes predetermined dots in the dot-matrix to be illuminated or extinguished so as to improve the overall continuity of the dot patterns defining the characters, yielding a more pleasing representation of those characters.

9 Claims, 15 Drawing Figures CHARACTER ADDRESS U..S Patent Nov. 18, 1975 .Sheetlof 10 3,921,164

0 6 0 G0 0 Q Q 0 .0 0. 0 O. 0 .0 0 .0 0 00 w 0 9 0 00.0000 0 0 O O O O 0...... ..0

00 0 0 0 a 0 006 0 60 0 0 0 0 6 0 0 0.0. 0 90$ 6 0 0 O O 0 O 0 0 0.0 0 0 000.... w 0 O. .0 00 O. O 0 O O O 00 o O 0. O O 00.00 D O O O .Q...

o o 00 Q a o o a o o 0 0 0 o o o 0 o o o 0 0 o 0 o 0 0 o 0 0000 o o o 0 00 de 00 o o o 0o 00 0&000

U.S. Patent Nov. 18,1975 Sheet3of10 3,921,164-

DZI 22 23 il,j-l i|,j i-l,j+|

O b Cl b D D C d 33 ml 0 d I,I+I

4| 42 43 i+l,jl i+l,j i+l,j+l

Hg. 4 Fig. 5

.. I I. Q.

5x? SMOOTHING RESOLUTION APPLIED u b c .0 O. O. O.

0-000 00 000060000 00000 on .0 .0.0 6. O... 0%

5 x 7 BASIC MODIFIED RESOLUTION SMOOTHING SMOOTHING Fig, 7

US. Patent Nov. 18, 1975 Sheet4of 10 3,921,164

ijd

ijc

ijb

iju

US. Patent Nov. 18, 1975 SheetSof 10 3,921,164

TO DISPLAY LSB COLUMN COUNTER CONTROL ROW COU NTER ROW 8 ELECT CODE (3-BITS) LOGICAL "o" (FIG. 8)

OUTPUT SELECTOR SMOOTHING CIRCUIT CHARACTER ADDR ESS US. Patent Nov. 18, 1975 Shet6of 10 3,921,164

XFER ROM ROW 0 TO 74 N-REG.

XFER N TO P- REG. XFER ROM ROWI 76 TO N-REG.

CL. ROW 8 COL. COUNTER CL. L-REG.

-*-- LIGHT 0R CLEAR DOT SHIFT L, P YES a N LEFT T DI-ABIT D) EN ROUN [84 No co| COUNT c o| .couNT YES {I00 SHIFT L,P&N

l-BIT (END AROUND) 92 90 ROW COUNT +1 CL.COL. COUNT ROW COUNTER +l CL.COL. COUNTER XFER P TO L N TO P ROM TO N U.S. Patent Nov. 18, 1975 Sheet70f 10 3,921,164

Fig. H

CLEAR ROW COUNTER LOAD P REG. WITH ROM ROW 0 CLEAR L REG.

DISPLAY ROW OF DOTS LOAD "L REG. WITH CONTENTS OF P LOADRP REG. WITH I74 ROM OUTPUT ROW COUNT US. Patent Nov. 18, 1975 Sheet8of 10 3,921,164

1T5 0 10 NS ROW SELECT BITO ROW SELECT BIT 2 ROW SELECT BIT l COLUMN 3 OUTPUT SELECTOR SMOOTHING CIRCUIT COLUMN 2 OUTPUT SELECTOR COLUMN I OUTPUT SELECTOR DISABLE SMOOTHING CIRCUIT COLUMN 0 OUTPUT SELECTOR 6-BIT CHARACTER CODE US. Patent Nov. 18, 1975 Sheet9ofl0 3,921,164

a COLUMN 4 COLUMN 5 COLUMN 6 COLUMN 7 I OUTPUT OUTPUT OUTPUT OUTPUT SELECTOR SELECTOR SELECTOR SELECTOR SMOOTHING CIRCUIT SMOOTHING CIRCUIT [34 no cocoa on 0 mac LOGICAL 0 IF I ROW COUNT zlz LOAD P a L-REG's CONTROL CLEAR L-REG.

ROW COUNTER CLEAR I64 INCREMENT Fig. l/ b US. Patent Nov. 18,1975 Sheet 10 0f,10 3,921,164

a COLUMN 8 COLUMN 9 OUTPUT OUTPU SELECTOR CTOR SMOOTHING CHARACTER GENERATOR FOR A HIGH RESOLUTION DOT MATRIX DISPLAY BACKGROUND OF THE INVENTION This invention relates generally to information display devices suitable for use with digital processing equipment and more specifically to an improved character generator for use in a dot-matrix type alphanumeric display device.

The earliest digital data processing systems included as a peripheral unit a printer mechanism for generating hard copy of data developed within the computing system. Such devices were normally operated off-line with respect to the data processing system because of their inherent slow speed of operation. More recently, in order to enhance the man-machine interface and in applications where it is unnecessary to have hard copy print-out of the information, effective use has been made of electronic display devices which operate online. Being electronic in nature, the inertia producing elements of the earler printer mechanisms have been replaced with inertialess electronic circuitry in the form of a character generator which, when coupled to a cathode-ray oscilloscope or other electronic'display device, can cause alpha-numeric characters to be visually presented.

The two principal types of character generators disclosed in the prior art are the so-called stroke generator and dot-matrix display generator. In the former, an alpha-numeric character is presented by generating incremental line segments which when connected together create a visual presentation of a desired character. In the dot-matrix type display, characters are formed by sequentially generating a series of discrete spots at predetermined coordinate locations to thereby form an image of the character. The present invention is concerned with an improved character generator for a dot-matrix type display.

In typical prior art dot-matrix display devices, the matrix in which each character is formed may comprise 35 discrete dot locations arranged in seven rows of five possible dot locations. This is commonly referred to as va 5 X 7 dot matrix. The conventional method of generating the 35 binary signals corresponding to the states of the 35 elements in the display, makes use ofa Read- Only Memory (ROM). The character set to be displayed is normally respresented by a character code which is a set of binary encoded words or bytes, generally about 6 bits in length. Each character code is used to address a unique section of the ROM. Each of the discrete sections of the ROM contains 35 data output bits which correspond to the 35 elements of the 5 X 7 dot-matrix display. Each of the 35 output databits of a particular ROM section is programmed to a binary l or 0 state, according to whether or not the corresponding display element is to be illuminated or not. For a particular section of the ROM, the 35 data bits are then programmed for the purpose of displaying the particular character whose code corresponds to that section of the ROM.

Those skilled in the art will recognize that many types of ROM devices have been disclosed in the prior art.

For example, semiconductor diode matrices, magnetic core arrays, and other types of componentry have been interconnected to provide a fixed pattern of readout signals as an output upon interrogation. These ROM devices provide a means of retrieving a large amount of digital information which was previously permanently stored (i.e., written) into the memory during the manufacturing process. More recently, socalled metal oxide semiconductor (MOS) technology has provided an ec onomical means for implementing ROMs with fieldeffect transistors for use in character and symbol generating devices.

Using a 6bit character selection code, which permits the selection of one out of 64 possible characters, the ROM may be organized as 64 words of 35 bits each. A more conventional approach, however, is to reduce the number of parallel outputs to five or seven, corresponding to a single row or column of the matrix, respectively. This approach reduces the number of connections on the ROM and allows it to be integrated on a single monolithic chip. As an example, the resulting ROM might have a 6-bit address for the character code, and an additional 3-bit address for selecting one of the seven rows of the 5 X 7 matrix. Using this approach, only a single row of the matrix (i.e., 5 bits) is available simultaneously from the ROM device at any one time. The seven rows must then be read sequentially from the ROM in order to obtain the 35 bits required by the standard 5 X 7 dot-matrix display.

With only 35 discrete spots which may be lit or unlit to define a character, many of the characters tend to lack resolution making it somewhat difficult to read and detracting from the normal expected appearance of standard alphabetical and numeric symbols. In order to improve the resolution of a dot-matrix display, the immediate solution which would occur to one of ordinary skill would be to increase the size of the ROM so that more dots would be used in defining each character. For example, one might consider adopting a 10 X 14 matrix which doubles the number of rows and columns of the conventional 5 X 7 matrix. In doing so, the size of the ROM would have to be quadrupled in order to gain the the desired improvement in the shape and sharpness of the characters.

In accordance with the teachings of the present invention, the number of dots comprising a character matrix may be quadrupled with no attendant increase in the size of the ROM employed in the character generator. In the practice of the present invention the 35 dots normally comprising a 5 X 7 character matrix are each considered to be a group of 4 dots, such that the 4 dots in each group are mutually adjacent, either vertically,

.horizontally or diagonally. As such, the resulting 10 X 14 display matrix can then be used to display characters as if it were a 5 X 7 matrix. In generating the 10 X 14 character, it is required that all the dots within a 4-dot group that corresponds to a lighted dot in the 5 X 7 matrix must also be lighted. This technique alone provides a substantial improvement in the appearance of the character over that which can be achieved through the use of the conventional 5 X 7 matrix. Additionally, the present invention provides a means for selectively lighting certain dots in the normally unlit 4-dot groups so as to fill in gaps which would otherwise appear in the character, thereby increasing the resolution of the displayed character. All this is accomplished without a need for increasing the memory capacity of the ROM.

In carrying out the present invention, circuitry is provided which will cause a selected dot in a normally unlit 4-dot group to be lighted when both of the adjacent 4-dot groups are lighted and the adjacent diagonal 4-dot group is not lighted, all as determined by the information stored in the ROM. Under control of a row 3 counter and a column counter associated with the ROM, binary signals representative of the lighted or unlighted condition of each dot in a row of a X 7 matrix are sequentially read out from the ROM into a set of shift registers which provide outputs from selective stages thereof to the input of a smoothing circuit. The smoothing circuit contains Boolean logic elements which operate upon the input signals thereto to determine whether the dots in a selected 4-dot group should be lighted or extinguished in order to display the particular character that has been selected. Thus, the invention allows higher resolution characters relative to 7 ROM size than previously available.

OBJECTS It is accordingly an object of the present invention to provide an improved character generator for a dotmatrix type digital display device.

Another object of the invention is to provide a method and apparatus for markedly improving the appearance of characters formed by a dot-matrix character generator without an attendant increase in the storage capacity of the Read-Only Memory used therein.

Still other objects and advantages of the invention will become apparent to those skilled in the art upon a reading of the following detailed description of the preferred embodiment when considered in connection with the accompanying drawings in which:

FIG. 1 illustrates the 64 character subset of the American Standard Code for Information Interchange (ASCII);

FIG. 2 illustrates the 5 X 7 dot-matrix format used for displaying the letter S of the ASCII subset;

FIG. 3 illustrates the manner in which the letter S is formed in accordance with the teachings of the present invention;

FIG. 4 illustrates the manner of identifying a particular cell of a four-dot group located on a display;

FIG. 5 illustrates a manner of identifying any one of the possible cell locations on a M X N matrix;

FIG. 6 illustrates the shape of the charater C with and without basic smoothing applied;

FIG. 7 illustrates the ampersand character on a X 14 matrix display using 5 X 7 resolution (no smoothing), with basic smoothing and with modified smoothing applied, respectively;

FIG. 8 is a logic drawing illustrating the smoothing circuit utilized in the preferred embodiment of FIG. 9;

FIG. 9 is a block diagram of the preferred embodiment of the present invention;

FIG. 10 is a flow diagram illustrating the sequence in which various commands are generated by the control circuit illustrated in FIG. 9;

FIGS. 11a, 11b and 110 when arranged as shown in FIG. 11 depict an alternative embodiment of the invention; and

FIG. 12 is a flow diagram illustrating the operation of the embodiment of FIG. 11.

DETAILED DESCRIPTION Illustrated in FIG. 1 is the 64 character subset of the American Standard Code for Information Interchange (ASCII) which illustrates the manner in which a series of discrete dots arranged in a 5 X 7 matrix can be used to represent various alpha-numeric characters. To implement a character generator for presenting this ASCII character grouping would require a ROM having a capacity of 2,240 bits (5 X 7 X 64). Each bit in the memory is set to a binary l or 0 depending uponwhether the dot at that coordinate location is to be lit or unlit, respectively, in forming a given character. Therefore, for a particular section of the ROM, the 35 data bits are programmed for the purpose of displaying a particular character whose address code corresponds to that particular section of the ROM.

For a 6-bit character code, which allows the selection of any one out of a total of 64 characters, the ROM may be organized so as to include 64 words of 35 bits each. As was mentioned, the more conventional approach is to reduce the number of parallel outputs to 5 or 7 (corresponding to a single row or a single column of the matrix, respectively). By doing so, the number of connections on the ROM is reduced, allowing semiconductor integrated circuit fabrication of the ROM. In this latter arrangement, the ROM is addressed by a 6-bit code for selecting a particular character from the group of 64 possible characters. In addition, three other bits of address information are supplied to the ROM for the purpose of selecting one of the seven rows of the 5 X 7 matrix. Following this approach, only a single row of the matrix (i.e., 5 bits) is available simultaneously from the ROM. All seven rows must be read sequentially from the ROM in order to obtain the 35 bits included in the 5 X 7 dot matrix display.

FIG. 2 illustrates the letter S as it would be displayed on a conventional 5 X 7 matrix. The filled-in circles represent the coordinate locations in the 5 X 7 matrix where the dot is illuminated, whereas the open circles represent the coordinate locations where the dot is extinguished. It is to be observed that the continuity of the character departs from the conventional Arabic letter in those areas of greatest curvature and that the overall appearance of the character can be improved by including additional lighted spots. For example, next consider the higher resolution dot-matrix display illustrated in FIG. 3. The matrix display of FIG. 3 utilizes dots in forming the character (a 10 X 14 matrix). This matrix has four times the number of dots as does the 5 X 7 matrix shown in FIG. 2. One obvious way of obtaining the higher resolution illustrated in obvious way of obtaining the higher resolution illustrated in FIG. 3 would be to quadruple the size of the ROM used in the character generator portion of the dot-matrix display. The present invention provides a method and apparatus that will yield the improved character resolution without the need for increasing the storage capacity of the ROM from that which is required to present a 5 X 7 dot-matrix display.

As is shown in FIG. 3, the 10 X l4 dot-matrix is partitioned into 35 groups of 4 dots each, such that the 4 dots in each group are mutually adjacent in the vertical, horizontal or diagonal direction. Since the 4-dot groups form a 5X 7 matrix, the 10 X 14 display matrix can therefore be used to display characters as if it were a 5 X 7 matrix.

Again referring to FIG. 3, it is to be noted that the positions of the 35 dots in the conventional 5 X 7 matrix have been identified by two digit numerals, the first digit identifying the row position and the second digit identifying the column position. Furthermore, the single dots within each 4-dot group are designated by the lower case letters a, b, c and d, the letter a corresponding to the upper left hand corner, the letter b-corresponding to the upper right hand corner, the letter 0 corresponding to the lower left hand corner and the letter d corresponding to the lower right hand corner.

Using these alphabetical and numerical identifiers it is possible to pin-point any one of the I40 individual dots in the matrix.

With these positional definitions in mind, an algorithm will next be described which will generate characters for a X 14 dot-matrix display using a ROM that is programmed (prewritten) for a 5 X 7 dot-matrix display. The algorithm will result in a generation of a character set that has improved resolution over that which can be achieved with a 5 X 7 matrix character set.

In generating the 10 X 14 character, it is a requirement that all of the dots within a 4-dot group that corresponds to a lighted dot in the 5 X 7 matrix must be lighted. It may initially be assumed that the remaining dots (those in 4-dot groups associated with the unlighted dots of the 5 X 7 matrix) are not lighted. These unlighted dots will then be examined according to the algorithm to be developed and a selected number of these dots may be lighted in order to improve the resolution, i.e., the shape, of the character.

FIG. 4 shows the four dots within the 4-dot group, D For simplicity, these have been designated as a, b, c and d in accordance with the above definition rather than as D D D and D Also illustrated in FIG. 4 are the 4-dot groups which surround D Assume now that a5 X 7 matrix ROM has been utilized to determine which 4-dot groups in the IQ X 14 matrix must be lighted for displaying some arbitrary character. Assume further that the 4-dot group D corresponds to an unlighted dot of the 5 X 7 matrix. All of the unlighted dots will now be examined to determine if lighting some of these dots will improve the appearance of the character. The basic approach or algorithm for lighting one of these dots requires that the dot be lighted if both of the adjacent 4-dot groups are lighted (as determined from the ROM), and if the adjacent diagonal 4-dot group is not lighted (again as determined from the ROM). In accordance with the above rule, the dot D shall be lighted if the 4-dot arrays D and D are lighted, and if D is not lighted, as determined from the information stored in the ROM. If the logic signals representing the states of the 4-dot groups D D and D are also designated as D D and D respectively, and if the lighted state is defined as a logical l and the unlighted state a logical 0, then the signal for lighting the dot D can be exp r5ssed by the Boolean equation D320 D12 z: D23 Noting that the dot D would also be lighted if the signal D is a l, as determined by the ROM, the complete expression for lighting the d o t D is given by ub riz' zz D33 D2: In a similar fashion, equations for the remaining dots in the 4-dot group D can be expressed as:

an al 22 zl 32 azc al 42 E 32 am an 42 4: 32

With reference to FIG. 5 which shows an arbitrary 4-dot group D similar, but generalized, equations can be written for any of the dots in the I0 X 14 matrix as With respect to these general equations, a special situation arises when they are applied to a dot along the edge of the matrix. For example, consider the dot D in FIG. 3. The 5 X 7 dot D is adjacent on the left from dot D Since D is at the edge of the defined matrix,

there is no defined 5 X 7 dot adjacent to and directly below D However, if the matrix were extended by an additional 5 X 7 row (i.e., row 7), then the 5 X 7 dot adjacent and below D would be designated D Also, the diagonally adjacent 5 X 7 dot to D would be designated as D The terms D and D appear in the equation for determining whether or not D is to be lighted. This equation utilizes the equation given above for D where i+ 6 and j 4. Since the dot positions D and D are beyond the defined matrix, it can be assumed that these dots are unlit (i.e., D D-,., 0). Accordingly, in utilizing the above equations to determine the state of any dot on the edge of the 10 X 14 matrix, it is assumed that any dot position outside the defined matrix (i.e., any undefined dot position) corresponds to an unlit position. This is the same as assuming that the 5 X 7 matrix is extended by two additional rows (one above and one below the defined matrix) and by two additional columns (one at the left and one at the right of the defined matrix), where the dots in these additional rows and columns are always unlit.

Referring again to FIG. 3, it will be seen that the application of the foregoing smoothing algorithm will result in the illumination of selected dots in otherwise unlit 4-dot groups as indicated by the cross-hatched dots. When these selected dots are combined with the pattern which results when the 4-dot groups associated with the 5 X 7 matrix are illuminated, the discontinuities which would otherwise exist at the points of greatest curvature are filled in, thereby improving the appearance of the resulting character.

As a further example, FIG. 6 shows the character C as displayed on a 10 X 14 matrix with both 5 X 7 resolution and with the smoothing algorithm applied. The improvement is immediately obvious.

The basic smoothing algorithm that has been described improves the shape of characters by rounding out or smoothing the curves in the character. Some characters, however, can be improved still further by the addition of a refinement to the basic algorithm. Consider, for example, the ampersand character (&"). FIGS. 7a and 7b respectively show the ampersand as displayed on a 10 X 14 matrix for both 5 X 7 resolution and also as it results from the application of the basic smoothing algorithm described above. Although the basic smoothing algorithm may have improved the 5 X 7 ampersand, the resulting character is certainly far from the optimum obtainable with a 10 X 14 matrix. A better character results with a modification of the basic smoothing algorithm.

The basic smoothing algorithm as applied to the ampersand, has caused too many additional dots to be lighted over those lighted in the 5 X 7 resolution character. One possible modification of the algorithm to correct this would be to disable the lighting of all the dots in a 4-dot group which is not lighted in the 5 X 7 resolution character, and in which more than one dot would be lighted according to the basic smoothing algorithm. However, the approach to be described hereinbelow and which is implemented in the hardware design yet to be described is to examine the dots within each unlighted 4-dot group in some fixed sequence or according to some fixed priority, and when a single dot is lighted, as determined by the basic algorithm, then the remaining dots shall not be lighted. This modification results in a maximum of one dot being lighted in each 4-dot group that is not lighted in the 5 X 7 resolution character. The characters that result from this re- 7 finement of the basic algorithm depend on the priority assignment among the four dots within a group. Different characters may prefer a different priority assignment. It is apparent, however, that this modified smoothing algorithm can be implemented with a fixed priority assignment and that very good results are at: tainable.

There are 24 different priority assignments possible for the four dots within a single 4:d0t group, and there: fore, there are 24 different character sets theoretically possible for the modified smoothing algorithm. No at: tempt has been made here to determine which of these 24 priority assignments results in a best formed char; acter set since this determination is subjective at best.

In implementing the modified smoothing algorithm let it be assumed that the priority assignment for lighting the dots within a 4-dot group is given by the order d, c, a and b. That is, d has the highest priority, then c, then a and then b. Referring again to FIG. 5 for the def: inition of terms, the equations for lighting the dots within the 4 -dot group D,,- with the above priority as; signment applicable are:

Ud u DI. J+| m. 1 DIM. 1+1

uc I W The ampersand, as generated by the modified smoothing algorithm given in the above equations, is shown in FIG. 7(c). The improvement in appearance over that shown in FIGS. 7(a) and 7(b) is readily ap; parent.

By examining various character sets, it has been de: termined that the appearance of most characters is either improved or is unaffected by applying the modified smoothing algorithm to the 5 X 7 resolution char: acter. However, in the event that some particular character would be degraded by the effect of the smoothing algorithm, the smoothing algorithm must then be dis; abled.

This can be implemented rather simply by disabling the smoothing algorithm whenever the character code for such a symbol is encountered. To this end, a disable signal must be added to the smoothing terms of the equations for lighting the dots of the matrix. The B001: ean equations for lighting the dots within the 4:dOt group D so as to include the modified smoothing and the disable are then given as:

ud u' i. 1+1 DHI. 1 DIM. 1+1 Disable lk IE J-l H-l.) 1+1. j-l DIM isab e DIM u' r. 1: 1-1. 1' I i-l. i-l ljr D Disable uo i:+ r-i.1 DI. 1+1 I-l. in lju FIG. 8 illustrates by means of a logic diagram a cir cuit arrangement for implementing the above set of equations. A first rank of NAND gates, including gates 10, 12, 14 and 16, receive as inputs the digital information stored in the Read Only Memory indicative of whether a given spot in the X 7 resolution matrix is to be illuminated or not and combines the signals in ac: cordance with the set of equations presented immedi: ately above and provides an output to a second rank of NAND gates including gates 18, 20, 22 and 24. A sec: ond input to each of the gates 18, 20, 22 and 24 is also derived from the ROM output and is indicative of the binary state of a selected arbitrary dot (i.e., D,-,-) in the 5 X 7 resolution matrix. The resulting output appearing on the lines labeled D D D and D control the illumination of the individual dots in the 4 -dot group D,-,- of the 10 X 14 resolution matrix. It is to be noted that three of the outputs from the second rank of NAND gates, namely the outputs from gates 18, 22 and 24 are fed back as inputs to a set of positive NOR cir cuits 26, 28 and 30. The fourth NOR gate 32 has a fixed logical 0 at its corresponding inputs. The outputs fro... NOR circuits 26 through 32 are coupled as inputs to the first rank of NAND gates 10, 12, 14 and 16 and serve to determine the priority in which the four dots within a 4 dot group may be lighted. As previously noted, when the modified smoothing algorithm was de scribed, there are 24 different priority assignments possible for the four dots. The priority assignment is determined by the manner in which the outputs from the gates 18, 20, 22 and 24 are fed back to the NOR circuits 26, 28, 30 and 32. Thus, by the proper selection of inputs to the NOR gates one is able to effect different priorities. The circuit illustrated in FIG. 8 affords high: est priority to dot, d, in that if the input conditions are such that dot, d, is to be lighted, the signal appearing at the output of NAND gate 24 is fed back to inhibit NAND gates 10, 12 and 14. Dot, b, has lowest priority in that the output from NAND gate 20 has no control over the inhibiting of any of the NAND gates 10, 12, 14 or 16.

The disable signal applied to one of the inputs of each of the NOR circuits 26, 28, 30 and 32 provides a means for eliminating any smoothing in the 10 X 14 matrix and, as mentioned above, would be active when the character code for certain symbols are detected where the appearance of the character is degraded by smooth;

ing.

Although the circuit of FIG. 8 could be repeated for each 4 dot group of the 10 X 14 dot matrix display (i.e., 35 times), this approach would be overly costly and is generally not required. For many cases, such as when the display media is a cathode-ray tube or a plasma gas panel, only a single dot of the matrix is lighted (or cleared) at any one time. For such an appli: cation, then, only a single circuit such as shown in FIG. 8 is required.

FIG. 9 illustrates by means of a block diagram the circuitry used in a display for generating the signals for lighting a selected dot. In a cathode-ray tube type dis: play, the circuit of FIG. 9 would be used to control the blanking or unblanking of the electron beam as it scans the face of the CRT. In a plasma panel type display, the circuit of FIG. 9 would be used to control the on-off condition of a selected spot. Included within the char: acter generator circuit of FIG. 9 is a conventional Read-Only Memory (ROM) 34 which may be imple: mented in any number of well known ways. Unalterably stored in the ROM 34 is the information needed to de: fine the state of each four -dot group comprising the characters to be displayed. For purposes of example only, assume that the ROM 4 is constructed to store the 63 characters illustrated in FIG. 1 as well as a blank or space character. Also assume that each of the char: acters is defined by a 5 X 7 matrix (5 columns by 7 rows). The information stored at each discrete location will then define whether a dot corresponding to that location is to be illuminated or not. For example, if a bi nary O is stored at a given coordinate location in a char: acter matrix the dot corresponding to that location is off whereas if the state of the ROM element at that co ordinate location is a binary l the dot associated therewith is to be lighted.

Entering at the bottom of the ROM 34 are six input lines, indicated generally by the numeral 36. These lines are adapted to receive a 6-bit character code which acts as an address for selecting any one of the 64 possible characters stored in the ROM 34. This same character address is applied by way of conductors 38 to the input of a disable detect circuit 40. The disable detect circuit 40 compares the incoming address with one or more fixed code combinations and if equality is detected, an output signal is produced on the conductor 42. As such, the disable detect circuit 40 may comprise an associative memory or plural comparators, various arrangements of which are well known in the art.

Once a given character has been selected for display, each row of the 5 .X 7 matrix is sequentially scanned by means of the output from the control network 44, causing the 5 bits of information associated with a given row to appear on the output lines from the ROM labeled column through column 4 one after the other.

Under the control of a strobe or clock signal generated by control 44, the data for the row of the selected character being addressed is entered into a first left circular shift register 46, herein termed the N-Register. The outputs from the N-Register 46 are connected to the inputs of a second left circular shift register 48, termed the P-Register. Similarly, the output from the individual stages of the shift register 48 are connected to the inputs of a third left circular shift register 50, termed the L-Register. The transfers from the N-Register to the P-Register and from the P-Register to the L- Register are all gated transfers and occur when an appropriate clock enable signal is applied to them from the control network 44. The left shifting of the information in the registers 46, 48 and 50 occurs upon the generation of an appropriate left shift command from the control network 44. Similarly, control 44 may generate pulses at appropriate times to clear the N-Register and the L-Register by producing a pulse on the clear lines 52 or 54.

In order to step through the selected matrix on a serial dot-by-dot basis, a pair of binary counters including row counter 56 and column counter 58 are interconnected with the control 44. Where the ROM 34 stores character information with 5 X 7 resolution while it is desired that the resulting display provide X 14 resolution, the column counter 58 must be capable of registering the counts from 0 through 9 while the row counter 56 must be able to register the counts 0 through 13. In each instance the row counter 56 and the column counter 58 is incremented by clock pulses generated within the control network 44. Furthermore, the counters 56 and 58 are able to be cleared by commands generated by control 44.

It is to be noted that in addition to the five parallel information bits fed into the N-Register 46 from the ROM 34, there is a sixth input line thereto which is always in the logical 0 state. The reason for this input is that in applying the smoothing algorithms a problem would seem to arise for dots which are along the edge of the 10 X 14 matrix. As has been previously described, by assuming that the matrix is extended by additional rows and columns of 4-dot groups which are not lighted this problem is resolved. The logical zero input to the N-Register 46 simulates the unlighted state for the columns adjacent to the edges of the 10 X 14 matrix.

The left-most three output bits of each of the registers 46, 48 and 50 are connected as inputs to the smoothing circuit 60 either directly or through inverter circuits 62, 64, 66 or 68. The smoothing circuit 60 may comprise the logic network illustrated in FIG. 8 of the drawings. As such, the legends appearing on the input lines to the smoothing circuit 60 in FIG. 9 correspond to the similar legends shown on the input lines to the logic network in FIG. 8.

The four output lines from the smoothing circuit 60 labeled D D D and D are applied as inputs to an output selector network 70. The selector network 70 is an array of AND gates which receive as inputs the outputs from the smoothing circuit 60 as well as the output from the least significant bits (LSBs) of both the row counter 56 and the column counter 58. The following table shows which of the four outputs from the smoothing circuit will be selected as a function of the state of the lowest order bits of the row counter 56 and column counter 58:

TABLE I LSB Row Count LSB Col. Count Selected Output 0 0 U 0 l D I 0 o I l D Now that the organization and manner of interconnection of various components comprising the character generator of the present invention have been described in detail, consideration will be given to its mode of operation To begin with it is assumed that the row counter 56 and the column counter 58 have been cleared. The digital computer or other device to which the character generator is connected applies a 6-bit character address code to the input line 36 of the Read-Only Memory 34. The character address code uniquely selects one of the 64 possible characters stored in the ROM 34 for presentation on a display panel, cathode-ray tube, or other suitable media. Next, the control network 44 applies a row select code to the ROM 34. As was mentioned, the bits comprising a row of the selected character in the ROM are read out in parallel, but sequentially row-by-row. After initializing the registers, the 3-bit row select code is equal to the row count shifted right l-bit position plus two so that the row counter must be incremented twice before a new row select code will be presented to the ROM 34.

In operation, the dots that are to be lighted (or cleared) are assumed to begin with D at the top left of the 10 X 14 matrix (FIG. 3). The sequence of dots then proceeds from left to right across the top row (i.e., D to D to D to D The sequence then goes to the left-most dot of the next lower row (i.e., D and proceeds from left to right across that row, and so on until the entire matrix is covered.

To aid in the understanding of the operation of the embodiment of FIG. 9, there is set forth in FIG. 10 a flow chart which illustrates the sequence in which various data transfers and commands are produced.

Upon initiation (block 72), control circuit 44 emits a clock signal to the N-Register 46, allowing the binary signals from the ROM indicative of the on-off condition of the 5 bits in row zero to be entered into the N-Register 46 (block 74). The leftmost bit of the 6-bit N-Register is loaded with a binary 0. Next, as indicated by the flow diagram block 76, this data contained in the N- Register 46 is clocked into the P-Register 48 as a result of the appropriate clock signal generated by the control 44. Following this step, the byte stored in row 1 of the selected character in the ROM is entered into the N- Register 46. The row counter, column counter and L- Register 50 are next cleared. The smoothing circuit 60 (as implemented with the logic of FIG. 8) will accept as inputs the outputs from the leftmost three bits of the shift registers 46, 48 and 50. It is to be noted that the upper three bits of the three shift registers form the 3 X 3 matrix corresponding to FIG. 5. With the row counter 56 and the column counter 58 both cleared, reference to Table I will show that the condition of the output selector 70 will indicate the correct state of the dot, D (where 1' andj 0). If this output is a 1, then D should be lighted, and if the output is a 0 then D should be cleared.

Next, the column count is sensed (block 80) and since zero is considered an even number, the control 44 will check to determine if the column count is equal to nine (block 82). Since it is not, the column counter is incremented (block 84) thus causing the output selector 70 to gate to its output the signal D indicating the correct state for the dot D Following the selection of D control 44 again senses the column count to determine if it is odd or even. When an odd count is detected, control 44 presents a shift command to registers 46, 48 and 50 causing a one position left shift with the bits falling off the left end being reinserted in their right ends (block 86). This-operation presents a new set of inputs to the smoothing circuit 60 and again, a check is made to determine whether the column count is equal to nine (block 82). The steps of incrementing the column counter and either left shifting or not left shifting depending upon whether the column count is odd or even results in each bit of row zero of the ROM being examined by the smoothing circuit for the purpose of determining whether the dots a and b in the 4-dot group are to be illuminated or not.

Once the column count reaches 9, the contents of the L, P and N-Registers are again left shifted one bit endaround (block 88) and a test is made to determine whether the row count is odd (block 90). With the row count equal to zero (an even number), the next step in the operation is for the control unit 44 to increment the row count and to clear the column count back to zero (block 92). The effect of this operation is to cause the selector 70 to output the signals corresponding to the correct states for dots c and d of the 4-dot groups associated with row 0 of the X 7 matrix. As the column count is advanced as previously described, the output of selector 70 indicates (sequentially) the correct states for the dots in row 1 of the X 14 dot-matrix. When the column count again reaches 9 and the state of the row count is examined (block 90), it will this time be found to be odd and a check is then made to determine whether the row count is equal to 13 (block 94). If not, the control 44 increments the row counter and clears the column counter and causes an inter-register data transfer so that the byte for the next row stored in the ROM will be entered into the N-Register 46 while the previous contents of the N-Register are transferred to the P-Register 48 and the prior contents of the P-Register 48 are entered into the L-Register 50 (block 96). The row count is again checked (block 98) and if the row count is equal to 13, the N-Register is cleared. This is done in order that the extended row below the 5 X 7 matrix of 4-dot groups is taken to be all 0s (corresponding to the unlit state). Then the flow chart returnsto block 78 and the sequence previously described is repeated, moving across the 10 X 14 matrix from left to right and from top to bottom until a row count of 13 is detected at block 94. Once this condition is detected, the display of the entire character on a 10 X 14 resolution with modified smoothing has been accomplished and the display cycle is terminated (block 102). A new character address can then be presented to the ROM 34, calling up a new character for presentation and reinitiating the control 44.

In applying the present invention to dot-matrix type electromechanical printers to improve the appearance of the resulting characters or to a visual display media where serial presentation of the individual four-dot groupings is too slow for the persistency of the media, it may be desirable to display or print all of the dot groupings in a given row simultaneously. FIG. 11 illustrates by means of a logic block diagram an alternate embodiment for doing so. More specifically, the circuit arrangement shown in FIG. 11 functions to simultaneously generate ten output signals which provide an indication of the correct state for each dot in a single row of dots of the 10 X 14 matrix.

As with the embodiment of FIG. 9, the arrangement of FIG. 11 employs a ROM 104 for storing the information needed to define the state of each four-dot group comprising the character to be displayed on a 5 X 7 matrix. A six-bit character code applied to the ROM 104 serves to uniquely select a given one of the plurality of character 5 X 7 matrices for printing or display. The five output lines from ROM 104 labeled column 0 through column 4 are connected to the gated input terminals of the P-Register 106, which in this embodiment need not have shifting capabilities. The five ROM output lines are also individually connected to first inputs ofa set of five AND gates 108, 110, 112, 114 and 116. The second, or enable, input of each of these AND gates is connected by a line 118 to the control network 120 and as will be further explained, will cause the gates to be disabled when the contents of the row counter 122 are greater than or equal to l2.

The outputs from the individual stages of the P-Register 106 are connected by line 124 to the inputs of corresponding stages of the L-Register 126 which is also a conventional binary number storage register without shifting capabilities. The L-Register 126 like the P-Reg ister 106 has gated inputs which are enabled by control signals on line 128 emanating from the network 120 in a manner to be described when the operation of the embodiment of FIG. 11 is presented.

Rather than employing only a single smoothing circuit such as shown in FIG. 8, the embodiment of FIG. 11 utilizes five such circuits, one for each column of the 5 X 7 matrix. These smoothing circuits are identified by numerals 130, 132, 134, 136 and 138. These smoothing circuits have the exact configuration as depicted by the logic drawing of FIG. 8 except that since there is a smoothing circuit for each column, the generalized column identifier letter,j, in FIG. 8 has been replaced with a specific column number 0, 1, 2, 3 or 4 in the drawing of FIG. 11.

The outputs from the AND gates 108 through 116 as well as from the individual stages of the P-Register 106 and the L-Register 126 are connected directly or coupled through an inverter circuit to the input terminals of the smoothing circuits through 138 in the manner shown.

The four outputs from each of the smoothing circuits are connected in pairs to the inputs of a set of output selectors which are controlled by the output from the least significant bit (LSB) of the row counter 122 such that when the row count is even, the a and b lines are selected and the c and d lines are unselected, but when the row count is odd, the c and d lines from each of the smoothing circuits, are selected and the a and b lines are not.

As in the embodiment of FIG. 9, the system of FIG. 11 is also provided with a Disable Detect Circuit 160 which receives as inputs the character code supplied to the ROM 104 and which generates a disable signal for the smoothing circuits 130 through 138 whenever the character code specifies a character whose appearance is degraded by the smoothing technique.

Now that the general organization and interconnection of the various components comprising the embodiment of FIG. 11 have been described in detail, consideration will now be given to its mode of operation. In explaining the operation, reference will also be made to the flow diagram of FIG. 12.

The circuit of FIG. 11 operates such that the rows of the 10 X 14 matrix are sequenced from the top to the bottom of the matrix. During this sequencing, the binary row counter counts from to 13. At each state of the row counter the circuit of FIG. 11 outputs the correct state of the corresponding 10 X 14 matrix row. These outputs are then used by the display mechanism or printer to determine which dots of the selected row are to be lighted or printed. The ROM in FIG. 11 has as inputs a 6-bit character code which selects the character to be displayed and a 3-bit row code which selects one of seven rows of the 5 X 7 matrix character. Except during the initializing phase of operation (block 162 in FIG. 12) when the row address presented to ROM 104 is equal to zero, the row address to the ROM is equal to the row count in counter 122 shifted right one bit posi tion plus 1. When a particular row of a character is selected, the five outputs of the ROM 104 indicate the correct state for the dots in that selected row for displaying a 5 X 7 character. One row of the 5 X 7 matrix corresponds to two rows in the 10 X 14 matrix. When the 10 outputs from the selectors 140 through 158 in FIG. 11 indicate the states of the dots in a particular row of the 10 X 14 matrix display, the P-Register 106 contains the data corresponding to the states of the dots in the corresponding row of the associated 5 X 7 character. Also, the L-Register 126 contains the data corresponding to the 5 X 7 row immediately above the .5 X 7 row contained in the P-Register, and the output from the AND gates 108 through 116 indicate the states of the dots in the 5 X 7 row immediately below the 5 X 7 row contained in the P-Register. It is to be noted that the AND gates 108 through 116 are utilized to indicate that the states of the dots in the next lower 5 X 7 row are Os (i.e., unlit), when the P-Register 106 contains the data corresponding to the lowest defined 5 X 7 row (i.e., row 6). Accordingly, the AND gates are disabled when the row counter is equal to 12 or 13. Also, the L-Register 126 is initially cleared to indicate the unlit state for the 5 X 7 row above row 0. Each of the five smoothing circuits 130 through 138 in FIG. 11 determines the states for four dots in one of the 4-dot groups of the 5 X 7 row corresponding to the contents of the P-Register 106. The outputs of the smoothing circuits indicate the states for two rows of dots in the 10 X 14 matrix display. The selector circuits 140 through 14 158 are used to select outputs for only one row of the 10 X 14 matrix at a time. The selectors are controlled by the LSB of the row counter. When the LSB is a 0, the uppermost of the two 10 X 14 rows is selected and when the LSB is a l, the lower row outputs from the smoothing circuits are selected.

FIG. 12 is a flow chart giving the control sequence required for the circuit of FIG. 11 for generating a single 10 X 14 dotmatrix character.

When a new character code is presented to the ROM 104, the control network generates a signal on line 164 to clear the row counter to zero. Next control 120 generates an enable signal on line 166 to open the gates associated with the P-Register 106 such that the data defining the on or off states of row 0 of the selected character from the ROM 104 is entered therein. Control 120 then issues a clear signal on line 168 to clear out the previous contents of the L-Register 126 left over from the preceding character which had been displayed. The outputs from the AND gates 108 116, the P-Register 106 and the L-Register 126 when applied to the smoothing circuits 130 138 in the manner shown cause the smoothing circuits to produce signals on their a, b, c and d output lines indicative of whether the corresponding dot locations on the associated display media for columns 0 4 are to be lighted or unlighted or, in the case of a printer, whether a dot should be printed or not. At this time the row count is equal to 0 and, as such, selectors 140 through 158 select only the a and b lines and the column 0 through column 9 selector output lines bear signals indicative of the lit or unlit condition of the a and b dots in the 10 X 14 resolution matrix.

Following the display of the row 0 dots (block in FIG. 12), a check is made to determine if the row count is odd (block 172). Since 0 is considered an even number, the row count will be incremented (block 174) and a check made to determine whether the row count has reached 14 (block 176). If not, the incrementing of the row count will cause the selectors 140 through 158 to simultaneously gate out the signals from the smoothing circuits indicative of the lit or unlit condition of dots c and d for each column of row 1 of the 10 X 14 matrix (block 170).

The row count is again checked by circuits in control network 120 and this time it will be found to be odd, such that the control network 120 will generate a signal on lines 128 and 166 to load the L-Register 126 with the current contents of the P-Register 106 and the P- Register with the ROM output corresponding to the row address bits emanating from control network 120. This operation is represented by block 178 in FIG. 12. The row count is again incremented (block 174) and a check is performed to determine if the count is equal to 14. If not, the dots a and b of the selected row are again presented to the display media and this operation continues until the row count reaches 14, indicative of the fact that the entire character has been displayed or printed and the operation stops (block 180).

Thus it can be seen that the subject invention has been shown to allow a character generator for a 10 X 14 dot-matrix display with a ROM that is programmed for a 5 X 7 resolution display. This same invention allows a 14 X 20 dot-matrix display with a ROM program for a 7 X 10 resolution display. In general, an N X M display requires only N X &M resolution ROM. Accordingly, while the invention has been described with an exemplary embodiment of a given size, limitation to this specific arrangement is not intended and should not be inferred. Also, the role of the column and row can be interchanged such that a matrix of N rows of M columns can be handled where M N. It should also be understood that various omissions and substitutions and changes in the form and details of the preferred embodiment illustrated and its operation may be made by those skilled in the art without departing from the spirit of the invention. It is the intention, therefore, to be limited only by the scope of the following claims.

What is claimed is:

l. in a dot-matrix type character display of the type including a read-only memory for storing at addressable locations therein a plurality of matrices of binary signals each M rows by N columns, each signal indicative of the lighted or unlighted condition ofdiscretc dot groups to be displayed on a display medium in presenting a selected character from a subset of such characters, addressing means for selecting one of said plurality of matrices, and row selecting means for sequen tially reading out from said read-only memory in parallel the binary signals comprising the rows of said selected one of said matrices, the improvement comprising:

a. a first shift register connected to receive the parallel output signals from said read-only memory;

b. a second shift register connected to receive the parallel output signals from said first shift register;

c. a third shift register connected to receive the parallel output signals from said second shift register;

d. a smoothing circuit comprised of digital type logic circuits connected to receive, in parallel, the outputs from predetermined stages of said first, second and third shift registers for producing a lighting control signal indicating that a discrete dot on said display medium should be lighted when the binary signals stored in said read-only memory for said selected character dictate that either the dot group including said discrete dot is to be lighted, or both of the dot groups adjacent to said one discrete dot are to be lighted and the dot group diagonally adjacent to said one discrete dot is not to be lighted; and

e. output selector means connected to the output of said smoothing circuit and to said row selecting means for applying said lighting control signal to said display medium.

2. Apparatus as in claim I and further including a detector circuit having its input coupled to said addressing means and its output coupled to said smoothing circuit for disabling said smoothing circuit upon the detection of a predetermined character address.

3. Apparatus as in claim 1 wherein said row selecting means includes' a. a row counter for registering a count indicative of which of the M rows of binary signals is stored in said second shift register;

b. a column counter for registering a count indicative of which of the binary signals in the row indicated by said row counter is currently being displayed;

c. control means for periodically incrementing said column counter and developing a shift control signal each time said column count is odd, and

d. means for applying said shift control signal to said first, second and third shift registers.

4. Apparatus as in claim 3 and lurther including means in said control means for inci menting said row lie counter and clearing said column counter each timethe count in said column counter reaches 2N-l.

5. Apparatus as in claim 4 and further including:

a. means in said control means for producing gating control signals each time said row count is odd; and

b. means for applying said gating control signals to said first, second and third shift registers for tram ferring, in parallel, the contents of said second register to said third register, the contents of said first register to said second register and the contents of the row of said read-only memory selected by said row selecting means to said first register.

6. Apparatus as in claim 5 and further including:

a. means in said control means for terminating said incrementing means when said row count reaches 2M--l.

7. Apparatus as in claim 2 wherein said smoothing circuit comprises:

a. a first rank of NOR circuits equal in number to the number of dots in said discrete dot groups;

b. a first rank of NAND gates equal in number to the number of dots in said discrete dot groups, each having one input connected to the output of a different one of said NOR circuits in said first group and the remaining inputs coupled to the output from predetermined stages of said first, second and third shift registers;

c. a second rank of NAND gates each having a first input individually connected to the output from a NAND gate in said first rank of NAND gates and a second input of each coupled to a predetermined stage of said second shift register; and

(1. means connecting the outputs from the NAND gates in said second rank to the inputs of said NOR circuits in said first rank in accordance with a pre determined priority schedule.

8. Apparatus as in claim 7 and further including means coupling the output of detector circuit to an input of each of said NOR circuits in said first rank of NOR circuits.

9. In a dot-matrix type character display of the type including a read-only memory for storing at addressable locations therein a plurality of matrices of binary signals, each M rows by N columns, each signal indicative of the presence or absence of a visible indicia of discrete dot groups to be imposed on an observable medium by a utilization device in presenting a selected character from a subset of said characters, addressing means for selecting one of said plurality of matrices, and row selecting means for sequentially reading out from said read-only memory in parallel the binary signals comprising the rows of said selected one of said matrices, the improvement comprising:

a. a first register connected to receive the parallel output signals from said read-only memory;

h. a second register connected to receive, in parallel,

the outputs from said first register;

c. smoothing circuit means comprised of digital type logic circuits connected to receive the outputs from predetermined stages of said first and second registers for producing one or more control signals indicating that other discrete dots on said medium should be rendered visible when the binary signals stored in said read-only memory for said selected character dictate that either the dot groups including said discrete dots are to be rendered visible or both of the dot groups adjacent to a discrete dot are to be rendered visible and the dot group diago- 3,921,164 l7 l8 nally adjacent to said discrete dot is not to be rendered visible; and d. output selector means connected to the output of said smoothing circuit means and to said row selecting means for connecting said control signaHs) to said utilization device. 

1. In a dot-matrix type character display of the type including a read-only memory for storing at addressable locations therein a plurality of matrices of binary signals each M rows by N columns, each signal indicative of tHe lighted or unlighted condition of discrete dot groups to be displayed on a display medium in presenting a selected character from a subset of such characters, addressing means for selecting one of said plurality of matrices, and row selecting means for sequentially reading out from said read-only memory in parallel the binary signals comprising the rows of said selected one of said matrices, the improvement comprising: a. a first shift register connected to receive the parallel output signals from said read-only memory; b. a second shift register connected to receive the parallel output signals from said first shift register; c. a third shift register connected to receive the parallel output signals from said second shift register; d. a smoothing circuit comprised of digital type logic circuits connected to receive, in parallel, the outputs from predetermined stages of said first, second and third shift registers for producing a lighting control signal indicating that a discrete dot on said display medium should be lighted when the binary signals stored in said read-only memory for said selected character dictate that either the dot group including said discrete dot is to be lighted, or both of the dot groups adjacent to said one discrete dot are to be lighted and the dot group diagonally adjacent to said one discrete dot is not to be lighted; and e. output selector means connected to the output of said smoothing circuit and to said row selecting means for applying said lighting control signal to said display medium.
 2. Apparatus as in claim 1 and further including a detector circuit having its input coupled to said addressing means and its output coupled to said smoothing circuit for disabling said smoothing circuit upon the detection of a predetermined character address.
 3. Apparatus as in claim 1 wherein said row selecting means includes: a. a row counter for registering a count indicative of which of the M rows of binary signals is stored in said second shift register; b. a column counter for registering a count indicative of which of the binary signals in the row indicated by said row counter is currently being displayed; c. control means for periodically incrementing said column counter and developing a shift control signal each time said column count is odd; and d. means for applying said shift control signal to said first, second and third shift registers.
 4. Apparatus as in claim 3 and further including means in said control means for incrementing said row counter and clearing said column counter each time the count in said column counter reaches 2N-1.
 5. Apparatus as in claim 4 and further including: a. means in said control means for producing gating control signals each time said row count is odd; and b. means for applying said gating control signals to said first, second and third shift registers for transferring, in parallel, the contents of said second register to said third register, the contents of said first register to said second register and the contents of the row of said read-only memory selected by said row selecting means to said first register.
 6. Apparatus as in claim 5 and further including: a. means in said control means for terminating said incrementing means when said row count reaches 2M-1.
 7. Apparatus as in claim 2 wherein said smoothing circuit comprises: a. a first rank of NOR circuits equal in number to the number of dots in said discrete dot groups; b. a first rank of NAND gates equal in number to the number of dots in said discrete dot groups, each having one input connected to the output of a different one of said NOR circuits in said first group and the remaining inputs coupled to the output from predetermined stages of said first, second and third shift registers; c. a second rank of NAND gates each having a first input individually connected to the output from a NAND gate in said first rank of NAND gaTes and a second input of each coupled to a predetermined stage of said second shift register; and d. means connecting the outputs from the NAND gates in said second rank to the inputs of said NOR circuits in said first rank in accordance with a predetermined priority schedule.
 8. Apparatus as in claim 7 and further including means coupling the output of detector circuit to an input of each of said NOR circuits in said first rank of NOR circuits.
 9. In a dot-matrix type character display of the type including a read-only memory for storing at addressable locations therein a plurality of matrices of binary signals, each M rows by N columns, each signal indicative of the presence or absence of a visible indicia of discrete dot groups to be imposed on an observable medium by a utilization device in presenting a selected character from a subset of said characters, addressing means for selecting one of said plurality of matrices, and row selecting means for sequentially reading out from said read-only memory in parallel the binary signals comprising the rows of said selected one of said matrices, the improvement comprising: a. a first register connected to receive the parallel output signals from said read-only memory; b. a second register connected to receive, in parallel, the outputs from said first register; c. smoothing circuit means comprised of digital type logic circuits connected to receive the outputs from predetermined stages of said first and second registers for producing one or more control signals indicating that other discrete dots on said medium should be rendered visible when the binary signals stored in said read-only memory for said selected character dictate that either the dot groups including said discrete dots are to be rendered visible or both of the dot groups adjacent to a discrete dot are to be rendered visible and the dot group diagonally adjacent to said discrete dot is not to be rendered visible; and d. output selector means connected to the output of said smoothing circuit means and to said row selecting means for connecting said control signal(s) to said utilization device. 